This program is tentative and subject to change.
February 27 TEST
February 28
March 1
March 2
February 27 TEST
| Monterey Carmel | Oak | Fir | Bayshore Ballroom | |
| 9:00 – 10:30 | What is new in IP-XACT IEEE Std. 1685-2022? | Pushbutton Complete IP Generation |
Exhibitor Set Up | |
| 10:30 – 11:00 | Coffee Break (Gateway Foyer) | |||
| 11:00 – 12:30 | Applications of the UVM-AMS Standard | Static Signoff Best Practices – Learnings and experiences from industry use cases  | ||
| 12:30 – 13:30 | Lunch Sponsored byThe CHIPS Act and Its Impact on the Design & Verification Markets (Pine Cedar) | |||
| 13:30 – 15:00 | Hardware/Software Interface Formats – A Discussion  | A Methodology for Power and Energy Efficient Systems Design | ||
| 15:00 – 15:30 | Coffee Break (Gateway Foyer) | |||
| 15:30 – 17:00 | IEEE 1666-202x SystemC Sneak Peek | Democratizing digital-centric mixed-signal verification methodologies | ||
| 17:00 – 18:30 | Welcome / Exhibitor Reception (Bayshore Ballroom) | |||
February 28
| Monterey Carmel | Oak | Fir | Bayshore Ballroom | |
| 8:00 – 8:30 | Opening Session (Oak) | |||
| 8:30 – 9:00 | Coffee Break (Gateway Foyer) |
Exhibit Hall Open | ||
| 9:00 – 11:00 | Assimilate Machine Learning | Configuring UVM | Controlling UPF | |
| 11:00 – 12:30 | Poster Session (Gateway Foyer) | |||
| 12:30 – 13:30 | Lunch Sponsored byA Data-Driven Escape from the Verification Pit of Despair (Pine Cedar) | |||
| 13:30 – 14:30 | Keynote (Oak / Fir) | |||
| 14:30 – 15:00 | Coffee Break (Gateway Foyer) | |||
| 15:00-17:00 | Formal Restrained | Process RISC_V | Systematic Methodology | |
| 17:00 – 18:00 | TPC Reception – Invitation ONLY | |||
March 1
| Monterey Carmel | Oak | Fir | Bayshore Ballroom | |
| 8:00 – 9:00 | Panel: Systems are Evolving. Is Verification Keeping Up? (Oak / Fir) | |||
| 9:00 – 9:30 | Coffee Break (Gateway Foyer) | Exhibit Hall Open | ||
| 9:30 – 11:00 | Discovering Formal | Constraining Constraints | Completing Coverage | |
| 11:00 – 12:00 | Poster Ninja Warrior (Oak) | |||
| 12:00 – 13:30 | ||||
| 13:30 – 14:30 | Panel: AI-ML Algorithms are Transforming Verification: Separating Hype from Reality (Oak / Fir) | |||
| 14:30-15:00 | Coffee Break (Gateway Foyer) | |||
| 15:00- 16:30 | Analog/Mixed Signal Smorgasbord | Protecting Safety and Security | UVM Buffet | |
| 16:30 – 17:00 | Break | |||
| 17:00 – 17:30 | Best Paper Presentation (Bayshore Ballroom) | |||
| 17:30 – 18:30 | Exhibitor Reception (Bayshore Ballroom) | |||
March 2
| Cascade | Donner | Siskiyou | |
| 9:00 – 10:30 | Verification 2.0 – Multi-Engine, Multi-Run AI-Driven Verfication | Accelerate Coverage Closure from Day-1 with AI-driven Verification  | Evolutionary and Revolutionary Innovation for Effective Verification Management & Closure |
| 10:30 – 11:00 | Coffee Break (Bayshore Foyer) | ||
| 11:00 – 12:30 | A Wholistic Approach to Optimizing Your System Verification Flow | Growing need for End-to-end Protocol Verification Solutions from IP to Multi-die Systems | |
| 12:30 – 13:30 | Lunch Sponsored byUVM 1800.2-2020-2.0 Library Discussion (Sierra) | ||
| 13:30 – 15:00 | Understanding the RISC-V Verification Ecosystem | Verification of Inferencing Algorithm Accelerators
| Harnessing the Power of UVM for AMS Verification with XMODEL |
| 15:00 – 15:30 | Coffee Break (Bayshore Foyer) | ||
| 15:30 – 17:00 | Virtio based GPU Modeling | Getting Beyond ISA Compliance: Advanced Core/SoC Verification for RISC-V and other Beasts | |
