All times are listed in PST. Please note that the program is tentative and subject to change.
| 9:00 – 11:00 |
| Introduction to the 5 levels of RISC-V Processor Verification
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| 11:00 – 11:30 | Break | ||
| 11:30 – 12:30 | UVM-AMS: An Update on the Accellera UVM
| IP/SoC Design, Co-Verify, Co-Validate, Co-Everything in 90 Minutes!
| In-emulator UVM++ Randomized Testbenches for High-Performance Functional Verification
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| 12:30 – 13:00 | Break | ||
| 13:00 – 14:00 | An Overview of Security Annotation for Electronic Design Integration (SA-EDI) Standard
| Estimating Power Dissipation of End-User Application on RTL
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| 14:00 – 14:30 | Break | ||
| 14:30 – 15:30 | FuSa: An Update on the Accellera Functional Safety Standard
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| 15:30 – 17:00 | Networking | ||
| 8:30 – 8:45 | Opening Session | ||
| 8:45 – 9:00 | Break | ||
| 9:00 – 10:30 | Portable Stimulus Standard (PSS) | Mixed Signal Verification | Memory and Cache Verification |
| 10:30 – 12:00 | Posters | ||
| 12:00 – 12:30 | Break | ||
| 12:30 – 13:30 | Sponsor Sessions (Cadence & Imperas) / Networking | ||
| 13:30 – 14:00 | Break | ||
| 14:00 – 15:00 | KEYNOTE: Manish Pandey | ||
| 15:00 – 17:00 | Automating Stimulus Generation | Formal Verification 1 | Potpourri |
| 8:30 – 9:30 | Panel: The Meeting of the SoC Verification Hidden Dragons | ||
| 9:30 – 10:00 | Break | ||
| 10:00 – 12:00 | Regression Runtime and Debug Optimization | Formal Verification 2 | Automation and Other Languages |
| 12:00 – 13:00 | Panel: Going Faster – How to Cope with Shrinking Schedules and Increasing Complexity | ||
| 13:00 – 14:00 | UVM Birds of a Feather | ||
| 14:00 – 15:00 | Sponsor Sessions (AMIQ & Synopsys) / Networking | ||
| 15:00 – 16:30 | UVM: Knobs & Sequences | Low Power and UPF | Prototyping |
| 16:30 – 17:00 | Break | ||
| 17:00 – 17:30 | Best Paper Presentation | ||
