Introduction
Accellera’s IP-XACT Working Group has been developing a proposal for a revision of IEEE Std. 1685-2014. The proposal was handed over to the IEEE P1685 Working Group in late 2021 and was approved by IEEE Standards Association Board in September of 2022.

Abstract
This workshop addresses the IP-XACT user community including IP and SoC companies, EDA vendors, and research institutes to inform them about upcoming changes in IEEE Std. 1685. It also addresses examples of commercial tool support for these changes.
1. Overview of changes part 1:
a. Descriptions of parameterized register definitions in addition to register instances to enable reuse of such definitions.
b. Descriptions of operating modes in components that affect access of incoming and outgoing transactions, access properties of registers and register fields, and memory remapping.
c. Description of register field aliasing and broadcasting.
2. Semifore tooling usage / implementation of these new features
3. Overview of changes part 2:
a. Descriptions of HDL structures, unions and SystemVerilog interfaces in component ports, as well as design connectivity to support these concepts in netlisting.
b. Descriptions of analog and mixed signal properties in component ports to enable mixed-signal netlisting.
c. Descriptions of power domains in components and binding of power domains for component instances. This can be used to detect power domain crossings in the connectivity.
d. New: compatibility/mapping/connectivity rules updates
e. New: bus-definition packets
f. New: cpu memory-map
4. Arm IP usage / implementation of these changes
5. Overview of changes part 3:
a. Descriptions of run-time configurable component model parameters that are used by run-time configuration mechanisms such as SystemC CCI.
b. Support Representational State Transfer Application (REST) as transport layer for the Tight Generator Interface (TGI)

Richard Weber
CEO, Semifore Inc.

Edwin Dankert
Arm