The Accellera UVM-AMS Standard will define an architecture and methodology to extend UVM testbenches from digital-only applications to DMS/real-number and AMS designs as well. This technical workshop will walk the audience through a worked example that will illustrate the key pieces of this approach and give a preview of how this standard will expand the ecosystem for AMS verification to allow vendors and users to create and share compatible verification components and use them in existing UVM environments.

Tom Fitzpatrick
Siemens EDA, UVM-AMS Working Group Chair

Tim Pylant
Cadence Design Systems