We get so involved in polishing and refining what we know how to do that we sometimes forget to look up.  The systems we must verify aren’t just getting bigger. Architectures are becoming more sophisticated, as are system standards and value-chain expectations, all to meet the expansive goals we have in the cloud, 5G networks and smart everything. Now systems are splitting across chiplets, boards and wireless networks. All these trends have significant implications for verification and validation.

Products for fast moving markets don’t start with a nailed-down specification. Concurrent system design and verification is becoming more common, motivating continuous integration and ICE/digital twin validation. Some IPs come with unique needs: Validating RISC-V implementations to the open ISA standard; Verifying AI accelerators against a meaningful subset of huge test suites; Validating memory consistency in multi-core platforms, all the way to rack-level; Performance verifying NoC/mesh networks under a broad range of traffic demands. Non-functional metrics – power, safety, security – are familiar but becoming more complex, in part in the need to be validated together. FMEDA analysis is necessary but not sufficient for ASIL-D verification, while hacker ingenuity seems boundless (side-channel attacks, speculative execution …).

Verification teams want more application-centric tooling and methodologies to help address these needs. The Innovation in Verification series (published monthly in SemiWiki) was started three years ago to break out of our comfort zone by exploring research papers in hardware, software verification and systems verification and validation. Our goal is to stimulate, in an open forum, new ideas and product advances – to be ready to meet system needs as they appear. Panelists will discuss key problems for which they would like to see breakthroughs and promising ideas/research they would like to see explored further. We welcome audience feedback and ideas in the same vein.

Panelists include:

Paul Cunningham, Senior VP and GM, Cadence System Verification Group

• Dr. Paul Cunningham has served as Senior Vice President and General Manager of the System Verification Group (SVG) since March 2021, running the division since 2018. His responsibilities include logic simulation, emulation, prototyping, formal verification, Verification IP, and functional debug. Prior to this role, Cunningham was responsible for Cadence’s frontend digital design tools including logic synthesis and design-for-test.

Raúl Camposano, CTO Silvaco, Partner at Silicon Catalyst

• Dr. Camposano is Chief Technology Officer at Silvaco, responsible for driving and managing all software and design IP product development and technology roadmaps. He is also a partner at Silicon Catalyst, an incubator for semiconductor solutions, and lectures on EDA and Machine Learning Hardware at Stanford. He was previously an advisor to Applied Materials and the CEO of Sage Design Automation acquired by Applied Materials in 2020. He was also CEO of Nimbic, acquired by Mentor Graphics in 2014. Raúl spent most of his career with Synopsys, where he served as Chief Technology Officer, Senior Vice President, and General Manager.

Dave Kelf, CEO Breker Systems

• Dave holds the position of CEO of Breker. Prior to that, as Chief Marketing Officer Dave was responsible for all aspects of Breker’s marketing activities, strategic programs and channel management. Earlier, Dave served as vice president of worldwide marketing solutions at formal verification provider OneSpin Solutions. Dave was president and CEO of Sigmatix, Inc. He worked in sales and marketing at Cadence Design Systems, and was responsible for the Verilog and VHDL verification product lines. As vice president of marketing at Co-Design Automation and then Synopsys, Dave oversaw the successful introduction and growth of the SystemVerilog language, before running marketing for Novas Software, noted for the Verdi product line, which became Springsoft and is now part of Synopsys.

Alex Starr, AMD Corporate Fellow

• Alex Starr is an industry leader in hardware emulation, design verification and hardware-software validation strategy and methodologies. He introduced the mainstream usage of hardware emulation to all AMD products and his innovations have enabled AMD to continue executing on its technology roadmap and enhance its leadership position within the industry. Alex is responsible for the corporate Shift Left Initiative, with a goal of accelerating AMD’s silicon bring-up, improving design quality and reducing time to market. He also leads AMD’s central methodology team that enables hardware emulation, FPGA Prototyping and Virtual Platform modeling company wide.

Sujata Ravi, VP Silicon Verification and Validation, Ampere

• Sujata has extensive leadership experience in the semiconductor industry in roles ranging from design, pre-silicon verification to post silicon validation and customer support. Prior to joining Ampere, she worked at Intel for 15 years in a variety of positions throughout the company. Most recently, she was responsible for pre-silicon verification with focus on emulation innovation and initiatives to “shift left bug findings” and reduce sample time to customers. While at Intel, Sujata also led a design verification, design automation and emulation team responsible for five generations of Xeon processors. She received an Intel Achievement Award for her work in driving “shift left” initiatives that helped reduce considerable amount of time to product readiness. 

Bernard Murphy, Advisor and SemiWiki will moderate

• Dr. Murphy is a freelance advisor and blogger on verification and IP at SemiWiki. Earlier he was VP of Engineering, later CTO at Atrenta (the SpyGlass company) from inception to acquisition by Synopsys.