Assimilate Machine Learning
- Identifying unique power scenarios with advanced data mining techniques as full SoC (System On Chip) level with real workloads
Amir Attarha, Siemens; Pankaj Chauhan, Siemens; Satish-Kumar Agrawal, Siemens; Gaurav Saharawat, Siemens; Diwakar Agrawal, Siemens - A Survey of Machine Learning Applications in Functional Verification
Dan Yu, Siemens EDA; Harry Foster, Siemens EDA; Tom Fitzpatrick, Siemens EDA - Exploring Machine Learning to assign debug priorities to improve the design quality
Vyasa Sai, Intel Corporation; Vaibhav Gupta, Intel Corporation; Fylur Rahman Sathakathulla, Intel Corporation
Configuring UVM
- The Untapped Power of UVM Resources and Why Engineers Should Use the uvm_resource_db API
Clifford Cummings, Paradigm Works, Inc.; Heath Chambers, HMC Design Verification; Mark Glasser, Cerebras - Avoiding Configuration Madness The Easy Way
Rich EDELMAN, Siemens EDA - Tree Data Framework for Code Generation: Application of Generating UVM Testbench for Complex Designs
Chenhui Huang, Tenstorrent Inc.; Yu Sun, Tenstorrent Inc.; Divyang Agrawal, Tenstorrent Inc. - Strategies to Maximize Reusability of UVM Test Scenarios in SoC Verification
Hyeonman Park, Samsung Electronics; Namyoung Kim, Samsung Electronics; Kyoungmin Lee, Samsung Electronics
Controlling UPF
- Hierarchical UPF Design – The ‘Easy’ Way
Brandon Skaggs, Cypress Semiconductor, An Infineon Technologies Company; Chris Turman, Cypress Semiconductor, An Infineon Technologies Company; Joe Whitehouse, Cypress Semiconductor, An Infineon Technologies Company - Automation for Early Detection of X-propagation in Power-Aware simulation verification Using UPF IEEE 1801
Tony Gladvin George, Ramesh Kumar, Kyuho Shim, Karan K, Wooseong Cheong, Byung Chul Yoo – Samsung Electronics - Power Models & Terminal Boundary: Get your IP Ready for Low Power
Progyna Khondkar, Cadence Design Systems; William Winkeler, Cadence Design Systems; Brandon Skaggs, Infineon Technologies - Successive Refinement of UPF Power Switches
Prabhakar S Ayyagari, Intel Corporation; William G Crocco, Intel Corporation
Formal Restrained
- FSM Minesweeper – Scalable Formal Verification Methodology for Detecting Hangs in Interacting FSMs
Anshul Jain, Intel Corporation; Achutha KiranKumar V M, Intel Corporation; Harbaksh Gupta, Intel Corporation; Shashwat Singh, Intel Corporation - Doing the Impossible: Using Formal Verification on Packet Based Data Paths
Doug Smith, Doulos - Deadlock Free Design Assurance Using Architectural Formal Verification
Bhushan Parikh, Intel Corporation; Shaman Narayana, Intel Corporation
Process RISC_V
- Automated Thread Evaluation of Various RISC-V Alternatives using Random Instruction Generators
Endri Kaja, Infineon Technologies AG; Nicolas Gerlin, Infineon Technologies AG; Dominik Stoffel, Technische Universität Kaiserslautern; Wolfgang Kunz, Technische Universität Kaiserslautern; Wolfgang Ecker, Infineon Technologies AG - RISC-V Security Verification using Perspec/Portable Stimulus
Siyan Li, MediaTek; Junxia Wang, Mediatek - Random testcase generation and Verification of Debug Unit for a RISCV Processor Core
Sneha Mishra, NXP Semiconductors; Lu Hao, NXP Semiconductors; Ajay Sharma, NXP Semiconductors; Afshan Anjum, NXP Semiconductors; Lucia Franco, NXP Semiconductors; Sourav Roy, NXP Semiconductors; Jeff Scott, NXP Semiconductors - The evolution of RISC-V processor verification: open standards and verification IP
Aimee Sutton, Imperas Software Ltd.; Lee Moore, Imperas Software Ltd.; Mike Thompson, OpenHW Group
Systematic Methodology
- What I Wish My Regression Run Manager’s Vendor Knew!
David Crutchfield, Infineon Technologies; Brian Craw, Infineon Technologies; Jason Lambirth, Infineon Technologies - Using a modern software build system to speed up complex hardware design
Varun Koyyalagunta, Tenstorrent - Regvue: Modern Register Documentation
Rob Donnelly, NASA Jet Propulsion Laboratory; Josh Geden, NASA Jet Propulsion Laboratory - What’s Next for SystemVerilog in the Upcoming IEEE 1800 standard
Dave Rich, Siemens EDA
Discovering Formal
- Demystifying Formal Testbenches: Tips, Tricks, and Recommendations
Shahid Ikram, Marvell; Mark Eslinger, Siemens - A Simulation Expert’s Guide to Formally Verifying Software Status and Interrupts
Neil johnson, ciena
Constraining Constraints
- Creating 5G Test Scenarios, the Constrained-Random way
Keshav Kannan, Intel; Eric Kim, Intel - Datagen: Python Constrained Random Test Stimulus Framework
Jonathan George, Microsoft; James Mackenzie, Microsoft - See the forest for the trees – How to effectively model and randomize a directed rooted tree structure
Harry Duque, Axis Communications AB; Lars Viklund, Axis Communications AB
Completing Coverage
- Improve emulator test quality by applying synthesizable functional coverage
Hoyeon Hwang, Samsung Electronics; Teaseong Kim, Samsung Electronics; Sanghyun Park, Samsung Electronics; Yong-Kwan Cho, Samsung Electronics; Dohyung Kim, Samsung Electronics; Wonil Cho, Samsung Electronics; Sanggyu Park, Samsung Electronics - Closing Functional Coverage With Deep Reinforcement Learning – A Compression Encoder Example
Eric Ohana, Queensland University of Technology, Australia – University of Bielefeld, Germany - GraphCov: RTL Graph Based Test Biasing for Exploring Uncharted Coverage Landscape
Debarshi Chatterjee, Nvidia Corporation; Spandan Kachhadia, Nvidia Corporation; Chen Luo, Nvidia Corporation; Kumar Kushal, Nvidia Corporation; Siddhanth Dhodhi, Nvidia Corporation
Analog/Mixed Signal Smorgasbord
- Take AIM! Introducing the Analog Information Model
Chuck McClish, Microchip Technology Inc. - Automated Modeling Testbench Methodology Tested with four Types of PLL Models
Jun Yan, Renesas Electronics; Josh Baylor, Renesas Electronics - SystemVerilog Real Models for an In-Memory Compute Design
Daniel Cross, Cadence Design Systems
Protecting Safety and Security
- Is Your System’s Security preserved? Verification of Security IP integration
Predrag Nikolic, Veriest Solutions - Complex Safety Mechanisms Need Interoperability for Validation and Close Loop for Final Metrics
Daeseou Cha, Samsung; Vedant Garg, Siemens EDA; Ann Keffer, Siemens EDA; James Kim, Siemens EDA; Woojoo Space Kim, Samsung Electronics - Early Detection of Functional Corner Case Bugs using Methodologies of the ISO 26262
Moonki Jang, Samsung Electronics; Sunil Roe, Samsung Electronics; Youngsik Kim, Samsung Electronics; Seonil Brian Choi, Samsung Electronics
UVM Buffet
- It’s Not Too Late to Adopt: The Power of UVM
Kathleen Wittmann, Rockwell Automation - UVM-SV Feedback Loop – The foundation of self-improving testbenches
Andrei Vintila, AMIQ Consulting; Sergiu Duda, AMIQ Consulting - Verifying RO registers: Challenges and the solution
Ivana Dobrilovic, Veriest Solutions
A Study on Virtual Prototyping based Design Verification Methodology
Woojoo Kim, Samsung Electronics; Kunhyuk Kang, Smasung Electronics; Seonil Brian Choi, Samsung Electronics
A UVM Reactive Testbench for Jitter Tolerance Measurement of High-Speed Wireline Receivers
Jaeha Kim, Seoul National University
Accelerated Verification of NAND Flash Memory using HW Emulator
Seyeol Yang, Samsung Electronics; Byungwoo Kang, Samsung Electronics; Dongeun Lee, Samsung Electronics; Jintae Kim, Samsung Electronics
Accelerating Functional Verification through Stabilization of Testbench Using AI/ML
Srikanth Vadanaparthi, Qualcomm; Pooja Ganesh, Qualcomm; Dharmesh Mahay, Synopsys; Malay Ganai, Synopsys
An Enhanced DV Approach for Effectively Verifying High Speed, Low Power MIPI-MPHY5.0 Designs
Eldhose PM, Samsung Semiconductor India Research; Suraj Shetty, Samsung Semiconductor India Research; Sagar Jayakrishnan, Samsung Semiconductor India Research; Kuntal Pandya, Samsung Semiconductor India Research; Parag S. Lonkar, Samsung Semiconductor India Research
Automated Connectivity Test Creation for System-in-Package Analog Mixed-Signal Verification
Samantha Pandez, Analog Devices, Inc.; Christopher Geen, Analog Devices, Inc.
Automation Methodology for Bus Performance Verification using IP-XACT
Taeyoung Jeon, Samsung Electronics Co., Ltd., Hwasung-si, Korea; Gunseo Koo, Samsung Electronics Co., Ltd., Hwasung-si, Korea; Youngsik Kim, Samsung Electronics Co., Ltd., Hwasung-si, Korea; Seonil Brian Choi, Samsung Electronics Co., Ltd., Hwasung-si, Korea
Check Low-Power Violations by Using Machine Learning Based Classifier
Chi-Ming Lee, Mediatek; Chung-An Wang, Mediatek; Cheok-Yan Goh, Mediatek; Chia-Cheng Tsai, Mediatek; Chien-Hsin Yeh, Mediatek; Chia-Shun Yeh, Mediatek; Chin-Tang Lai, Mediatek
Discover Over-Constraints by Leveraging Formal Tool
Dongsheng Ouyang, NVIDIA Corporation; Ray Zhang, NVIDIA Corporation; Lucus Liu, NVIDIA Corporation; Doris Yin, NVIDIA Corporation; Wayne Ding, NVIDIA Corporation
Do not forget to get your SystemC code covered with UVMC
Vishal Baskar, Siemens Industry Software Inc- Siemens EDA
Improvement of UVM Scenario Generation, Control and Reproducibility using Portable Stimulus (PSS) for IP Validation
Robert Martin, Intel Corporation; Alan Curtis, Intel Corporation; Gopinath Narasimhan, Synopsys; Qingwei Zhou, Intel
Leveraging UVM-based Low Power Package Library to SOC Designs
Shikhadevi Katheriya, Silicon Interfaces; Avnita Pal, Silicon Interfaces; Sastry Puranapanda, Silicon Interfaces
Pragmatic Formal Verification of Sequential Error Detection and Correction Codes (ECCs) used in Safety-Critical Design
Aman Kumar, Infineon Technologies
System-Level Power Estimation of SSDs under Real Workloads using Emulation
Sangmin Kim, Samsung Electronics Co., Ltd.; Kwanghyo Ahn, Samsung Electronics Co., Ltd.; Changhoon Han, Samsung Electronics Co., Ltd.; Hyunsik Kim, Samsung Electronics Co., Ltd.; Jaewoo Im, Samsung Electronics Co., Ltd.
UVM Based Mixed-Signal Verification of a Display PMIC Designed for OLED Display Applications
Vijay Kumar, Samsung Semiconductor India Research; Adnan Malik, Samsung Semiconductor India Research
Verification Macros: Maintain the integrity of verifiable IP UPF through integration
Amit Srivastava, Synopsys Inc; Shreedhar Ramachandra, Synopsys Inc
A HW and SW integrated power optimization approaches with power aware simulations at SOC
Eldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath; Samsung Semiconductors India Research
